Leveraging SRAM for Counterfeit Detection and Secure 3DIC Integration

Abstract

Within the evolving domain of electronics security and counterfeit detection, researchers have historically placed a strong emphasis on techniques rooted in the analysis and recovery of non-volatile memory elements. These approaches often rely heavily on persistent data storage features and external references, such as golden chips or trusted databases, to validate authenticity and identify anomalies in suspect hardware. In particular, counterfeit integrated circuits (ICs) identification has been largely constrained to methodologies that assume the availability of a golden sample or access to other external sources of ground truth. While effective in controlled environments, such dependency significantly hampers scalability and real-world applicability, especially in distributed or resource-limited contexts.

In contrast, the detection of recycled or tampered volatile memory components—most notably, static random-access memory (SRAM)—has received comparatively little scholarly and industrial attention. This imbalance in research focus stems, in large part, from the widespread assumption that volatile memories lose all stored data immediately upon power-down. As a result, it is commonly believed that such memories offer little to no utility in postmortem security analyses. The volatile nature of SRAM has led to the prevailing view that these components are unsuitable for forensic examination or for use in security primitives that require persistent traceability. Consequently, recycled or subtly modified SRAM-based devices often evade detection using traditional security screening methods, leaving a critical blind spot in current counterfeit detection frameworks.

This thesis directly challenges these foundational assumptions by introducing a comprehensive and forward-thinking methodology designed to detect recycled SRAM-based electronics without relying on external references or trusted baselines. By leveraging the subtle, yet repeatable, physical properties of SRAM cells that influence their power-up state under controlled conditions—including manufacturing-induced variations, process defects, and aging-related degradation—it becomes possible to derive device-specific signatures that persist beyond power loss. These signatures, when appropriately analyzed, provide a viable means of distinguishing authentic devices from recycled ones, even in the absence of traditional reference models. Experimental validation presented throughout this research demonstrates the feasibility and effectiveness of these proposed strategies under realistic conditions. Through a series of accelerated aging simulation experiments and SRAM state analyses, this work confirms that it is possible to detect recycled SRAM hardware without requiring any prior knowledge of its original, unaged behavior.

In addition to addressing the detection of recycled SRAM devices, this thesis further extends its contribution to the broader domain of hardware security by proposing an architecture for secure operation within heterogeneously integrated systems. With the increasing adoption of 2.5D and 3D integrated circuits, where dies from diverse fabrication origins are assembled into a single package, supply chain trustworthiness has emerged as a pressing concern. To this end, a high-level security concept is introduced that incorporates a whitelisting framework enabled by an SRAM-based logging mechanism. This logger passively monitors operational characteristics and verifies the legitimacy of chiplet activity against a pre-approved whitelist, thereby mitigating the risk posed by unverified or malicious components within the system-in-package. To strengthen the forensic and auditability aspects of this architecture, the design is further augmented with a blockchain-based ledger that records security-relevant events in an immutable and verifiable manner. The integration of blockchain technology ensures that tampering attempts or unexpected deviations from baseline behavior can be recorded transparently and traced back with cryptographic assurance.

By rigorously exploring and substantiating these novel concepts, this thesis makes a substantial contribution to the field of electronics security. It not only redefines the utility of volatile memory in security-critical applications but also opens new pathways for counterfeit detection that are both reference-free and scalable. Ultimately, this work advances the state-of-the-art in memory-based forensics, device lifecycle validation, and secure system integration, setting the stage for more resilient and trustworthy hardware ecosystems in future semiconductor supply chains.