High Speed Pipelined SAR ADC with Time Domain sub-Ranging Fine Quantizer

Abstract

Analog-to-digital converters (ADCs) stand as indispensable bridges, seamlessly connecting the tangible realities of the physical world with the boundless possibilities of the digitalized virtual world. In recent years, the successive approximation register (SAR) analog to digital converter (ADC) architecture has become the most popular candidate. However, due to the increase in signal processing speed and the advance of CMOS technology in support of the high-speed digital circuits, the performance requirements of the ADCs have been elevated, demanding resolution beyond 10bits and conversion speeds exceeding 1GS/s. In response, researchers have started exploring the integration of various ADC architectures, including pipeline, flash, and delta-sigma, to achieve the optimal balance of high-resolution, high-speed, and low power consumption. As a result, the hybrid pipelined SAR ADCs architectures have been widely adopted in variety of applications. In addition to expanding voltage domain architectures, time to digital converters (TDCs) start gaining attention because of its’ high linearity and low power consumption. Besides, due to its digital circuit implementations, the TDC conversion speed is significantly increased with the advance of the deep submicron CMOS technology. This dissertation explores the fundamentals of ADC designs and dives into the advanced theory of quantization in both voltage and time domains. Traditional ADC architectures and circuit implementations are thoroughly examined. Additionally, the fundamentals and architectures of time-to-digital converters (TDC) are presented. Various prototypes are included to analyze existing architectures and introduce the proposed hybrid pipelined SAR ADC with a time-domain sub-ranging fine quantizer. In this proposed work, a SAR ADC is implemented as coarse stage, and it is passively connected to three ring-TDCs. These ring-TDCs are operated as time-interleaved fine stages, utilizing self-generated three-phase non-overlap sub-clocks. This hybrid architecture, with the cross-domain implementation, finally achieves the desired high speed and low power consumption performances. Furthermore, the auto-aligned passive residue transfer solution significantly reduced the pipelining stage’s power consumption and guaranteed robust operation under process, voltage, and temperature (PVT) variations. The ADC prototype has demonstrated itself as an excellent solution for high-speed and low-power applications, with the capability to evolve alongside advancements in sub-micron technologies. The prototype not only proved that the cross-domain quantization (a combination of voltage and time domains) is an excellent candidate for the advanced communication systems, but also highlighted the advantages of implementing time-interleaved sub-stage in high-speed architectures, which relaxes the ADCs input buffer drivability requirements.