Circuit Techniques for Adaptive Threshold-Voltage Regulation and Digitally Assisted Frequency Synthesis

Abstract

This dissertation presents circuit techniques for adaptive threshold-voltage regulation and digitally assisted frequency synthesis in advanced CMOS technologies. The first part in-vestigates adaptive threshold-voltage regulation using the back-gate biasing capability of fully depleted silicon-on-insulator (FDSOI) CMOS technology. A closed-loop threshold-voltage con-trol system is developed to compensate for process and temperature variations by sensing the effective threshold voltage and adjusting the body bias accordingly. The proposed approach provides a circuit-level method for stabilizing device behavior over a wide temperature range, which is particularly important for low-temperature and cryogenic operation. Additional imple-mentations based on constant-current threshold sensing and system-level validation using an analog-to-digital converter are also discussed to demonstrate the applicability of the proposed threshold-voltage control technique. The second part focuses on the design of fractional-N phase-locked loops (PLLs) for digitally assisted frequency synthesis. To improve timing resolution and suppress quantization-induced phase error, a merged-mode digital-to-time converter (DTC) architecture is developed to combine coarse and fine timing control within a unified delay-generation path. A time amplifier is further incorporated to relax the DTC resolution requirement, while a least-mean-square (LMS)-based background calibration scheme is used to adaptively align the cancellation path and reduce the impact of digital-to-time conversion errors. These techniques enable digitally assisted timing generation with improved flexibility, calibration capability, and noise performance. Together, these two research directions explore the use of digitally assisted and adap-tive circuit techniques to enhance the performance, robustness, and scalability of mixed-signal systems. Although applied to different circuit domains, the presented work shares a common em-phasis on using calibration, feedback, and device-level programmability to address nonidealities that become increasingly significant in advanced CMOS design.