Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip
| Metadata Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Stroud, Charles | |
| dc.contributor.advisor | Nelson, Victor | en_US |
| dc.contributor.advisor | Singh, Adit | en_US |
| dc.contributor.author | Harris, Jonathan | en_US |
| dc.date.accessioned | 2008-09-09T22:33:44Z | |
| dc.date.available | 2008-09-09T22:33:44Z | |
| dc.date.issued | 2004-12-15 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10415/1028 | |
| dc.description.abstract | Built-In Self-Test configurations for the logic and routing resources present in the Field Programmable Gate Array core of a System-on-Chip is presented in this Thesis. These configurations completely test the Programmable Logic Blocks and Programmable Routing Resources present in the Field Programmable Gate Array Core. A vendorspecific CAD tool, Atmel System Designer software suite, is used in conjunction with custom design automation tools to generate a complete set of logic and routing BIST configurations for any size Atmel AT94K series FPGA core as well as any size Atmel AT40K series FPGA. | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | Electrical and Computer Engineering | en_US |
| dc.title | Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip | en_US |
| dc.type | Thesis | en_US |
| dc.embargo.length | NO_RESTRICTION | en_US |
| dc.embargo.status | NOT_EMBARGOED | en_US |